MEM suspended gate non-volatile memory

ABSTRACT

A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing floating gate to floating gate coupling and leakage current, and increasing data retention.

FIELD

The present disclosure relates generally to suspended gate memories andin particular the present disclosure relates to suspended gatenon-volatile memories.

BACKGROUND

In standard non-volatile memory, especially flash memory, data retentionis an important characteristic. In general, data retention failure isdue to charge loss from floating gates (i.e., storage nodes) of thememory. There are many causes of charge loss, including tunnel oxideleakage, detrapping, mobile ions in inter-dielectric layer, and thelike. These are all related phenomena of materials surrounding thefloating gate.

On the other hand, micro-electro-mechanical (MEM) moving electrodedevices are becoming more and more common. In a MEM device, the movingnode is used as a gate of a metal oxide semiconductor (MOS) transistor,and has a very sharp threshold.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art forimproved data retention in memories.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a side elevation view of a suspended gate non-volatile memorycell perpendicular to a control gate, and in a non-operation positionaccording to one embodiment;

FIG. 2 is a side elevation view of the suspended gate non-volatilememory cell of FIG. 1 in an operation position according to anotherembodiment;

FIG. 3 is a side elevation view parallel to a control gate of thesuspended gate non-volatile memory cell of FIG. 1;

FIG. 4 is a view of a read operation position of the memory cell of FIG.3;

FIG. 5 is a view of a program operation position of the memory cell ofFIG. 3;

FIG. 6 is a top view of a memory array of suspended gate non-volatilememory cells;

FIG. 7 is a cross-sectional view of the memory array of suspended gatenon-volatile memory cells taken along line 7-7 of FIG. 6;

FIG. 8 is a cross-sectional view of the memory array of suspended gatenon-volatile memory cells taken along line 8-8 of FIG. 7;

FIG. 9 is a functional block diagram of an electrical system having atleast one memory device with a memory array configuration according toone embodiment;

FIG. 10 is a functional block diagram of a memory module having at leastone memory device in accordance with another embodiment;

FIG. 11 is a side elevation view of another suspended gate non-volatilememory cell; and

FIG. 12 is a side elevation view of yet another suspended gatenon-volatile memory cell.

DETAILED DESCRIPTION

In the following detailed description of the embodiments, reference ismade to the accompanying drawings that form a part hereof. In thedrawings, like numerals describe substantially similar componentsthroughout the several views. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe present invention.

The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present disclosure is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

The embodiments of the present invention include a non-volatile memorywith a carrier storage node normally separated or floated from asubstrate and a tunnel oxide. For operation of the memory, for examplefor read, erase, or program operations, the carrier storage node ismovable to contact the tunnel oxide and substrate. Due to separation ofthe carrier storage node from the surrounding material in a normal,non-operating state, leakage current from the carrier storage node issuppressed, and data retention performance is improved. For purposes ofthis disclosure, a suspended gate structure is one in which a metal gateor gate structure is suspended over a substrate by supporting arms.Pull-in voltage on a pull-in/pull-out gate causes the suspendedstructure to deflect toward the substrate, and pull-out voltage on thepull-in/pull-out gate causes the suspended structure to deflect awayfrom the substrate.

A MEM suspended gate non-volatile memory cell 100 of one embodiment isshown in side elevation in FIG. 1. The cell 100 comprises a substrate102 having source 104 and drain 106 regions, and a tunnel oxide 108 overthe substrate 102, source 104, and drain 106 regions. A suspendedstructure 110 has a carrier storage node (or floating gate) 112, adielectric 114, and a control gate 116. The suspended structure 110 ismovable between a first position as shown in FIG. 1, with an air orvacuum gap 118 between the carrier storage node 112 and the tunnel oxide108, and a second position in which the suspended structure carrierstorage node 112 contacts the tunnel oxide 108 (shown in FIG. 2).

The motion of the suspended structure 110 between the first, or normalnon-operating, position, and the second, or operating position, iscontrolled by the application of certain potentials to variouscomponents of the memory cell 100. Referring now also to FIG. 3, in oneembodiment, the motion of the structure 110 is controlled in part by thevoltage applied to a pull-in/pull-out gate (PPG) 120. The PPG 120 isformed in the substrate 102 and is typically positioned as shown in FIG.3. Application of a voltage to the PPG 120, combined with voltagesapplied to the source, drain, control gate, and substrate, allow thecell to operate in various operational states, such as read, program,and erase. Pull-in operation is when the suspended portion 110 is in thesecond (or operation) position as described above, and pull-out is whenthe suspended portion 110 is in the first (or non-operation) position asdescribed above.

For example, one set of voltages for reading a non-volatile suspendedgate memory cell such as cell 100 applies 0 volts to the control gate116, substrate 102, and source 104, 1.0 volt to the drain 106, and −10volts to the PPG 120. This pulls in the suspended portion 110 to thetunnel oxide 108, and allows a data read of the carrier storage node112. This is shown in FIG. 4.

To program a memory cell such as cell 100, one set of voltages applies aprogram voltage (for example, 20 volts) to the control gate 116, 0 voltsto the PPG 120 and substrate 102, and either 0 volts to the source 104and drain 106 for a selected cell, versus 10 volts to the source 104 anddrain 106 for an unselected cell. This combination of voltages pulls inthe suspended portion 110 to contact the tunnel oxide, and injectselectrons 124 from an active area 122 into the carrier storage node 112,programming the cell 100.

To erase a memory cell such as cell 100, the source 104 and drain 106are left floating, the control gate 116 is biased to 0 volts, the PPG120 to −10 volts, and the substrate to 20 volts. This set of voltagespulls in the suspended portion 110 to contact the tunnel oxide 108, andejects electrons 124 from the carrier storage node 112 to the substrate102.

When no operations are to be performed on the cell, the suspendedportion 110 is separated from the tunnel oxide 108 by the gap 118, withthe PPG setting for pull-out of the suspended portion 110 from thetunnel oxide 108. The gap 118 provides increased data retention byseparating the carrier storage node 112 from surrounding materials thatcan be possible leakage locations.

The voltages discussed above with respect to read, program, erase, andno operation are one set of voltages applicable to use of memory cellssuch as memory cell 100 in a NAND configuration. Different read/programerase operations and voltages are used for other types of memory cells,for example, NOR flash.

Memory arrays according to various embodiments include a memory cellarray, such as a NAND flash array, NOR flash array, or virtual grandarray. Each memory cell has a bit line, source line, and control gatewhich is in an air gap or vacuum gap. Floating gate to floating gateinterference is reduced, and parasitic capacitance on bit lines and wordlines is reduced. High performance operation therefore is possible. Anarray of suspended gate MEM non-volatile memory cells is shown in FIGS.6, 7, 8, which show, respectively, a top view, a first cross-sectionalview, and a second cross-sectional view of an array 600 of non-volatilesuspended gate memory cells.

Referring to FIGS. 6, 7, and 8, an array 600 of non-volatile memorycells such as cells 100 is shown. The cells of the array have asuspended structure including a common control gate (control gateslabeled 616) for each of a plurality of wordlines of the array, eachwordline having associated with it a plurality of carrier storage nodes(floating gates) 612 controlled by the common control gate, andseparated therefrom by a dielectric 614. Bitlines run perpendicular tothe wordlines. A combination of voltages applied to the bitlines andwordlines allows operation of the array. Operation of the array issimilar to that of an individual cell, but since a common control gateis used, the voltages applied are different from those used foroperation of a single cell. Further, in an array configuration, certaincells are selected or unselected, and require select gates. The generaloperation of select gates in a NAND array is known and will not bediscussed further herein.

For operation of a non-volatile suspended gate array such as array 600,one set of voltages is as follows. For non-operation, that is when nooperations such as read, program, or erase are being performed on thearray, the array is maintained with all of the suspended portions of thecells in their pull-out position. In this configuration, the PPGs aregrounded.

In one embodiment, a set of voltages for operations on the array are asfollows. When a read operation is desired on a cell, the PPG 620 for thecell is biased to −10 volts. The source and well (substrate) are biasedto 0 volts, the bit line to 1 volts, and the select gates 626 and 628for source and drain are biased to 3.5 volts. For a selected cell, thecontrol gate associated with that cell is biased to 0 volts, and forunselected cells, the control gate is biased to 5 volts. This pulls inthe selected carrier storage node for a read operation on the selectedcell.

To program a memory cell of an array such as array 600, one set ofvoltages applies a program voltage (for example, 20 volts) to thecontrol gate of the selected cell, a pass voltage, that is the voltageapplied to non-programming word lines to allow their cells to act aspass transistors, (for example, 10 volts) to the control gate ofunselected cells, −10 volts to the PPG, 0 volts to the source selectgate and the substrate, 1.8 volts to the source, 2.5 volts to the drainselect gate, and either 0 volts (selected) or 1.8 volts (unselected) tobitlines, depending upon whether the cell is to be programmed or not.This set of voltages pulls in the selected carrier storage node forprogramming.

To erase a memory cell of an array such as array 600, one set ofvoltages leaves the bitline, source and drain select gates, and thesource floating, applies 0 volts to the control gates, −10 volts to thePPG, and 20 volts to the substrate or p-well of the array. This set ofvoltages pulls in the selected carrier storage node for an eraseoperation on the block to be erased.

It should be understood that the voltages described herein arerepresentative of voltages that are amenable to the operations of thenon-volatile suspended gate memories and arrays described herein, butthat other sets of voltages will also work for the operations of thevarious embodiments. Still further, it should be understood that otherarray structures, such as NOR flash and virtual grand array structuresare also amenable to use with the suspended carrier storage nodeembodiments described herein.

The suspended gate non-volatile memory cells and memory arrays describedherein provide, for example, good data retention, reduced floating gatecoupling, and reduced bitline to bitline coupling.

FIG. 9 is a functional block diagram of a memory device 900, such as aflash memory device, of one embodiment of the present invention, whichis coupled to a processor 910. The memory device 900 and the processor910 may form part of an electronic system 920. The memory device 900 hasbeen simplified to focus on features of the memory that are helpful inunderstanding the present invention. The memory device includes an arrayof memory cells 930 having suspended gate non-volatile memory cells suchas those shown in FIGS. 1-8 and described above. The memory array 930 isarranged in banks of rows and columns.

An address buffer circuit 940 is provided to latch address signalsprovided on address input connections A0-Ax 942. Address signals arereceived and decoded by row decoder 944 and a column decoder 946 toaccess the memory array 930. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends upon the density and architecture ofthe memory array. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device reads data in the array 930 by sensing voltage orcurrent changes in the memory array columns using sense/latch circuitry950. The sense/latch circuitry, in one embodiment, is coupled to readand latch a row of data from the memory array. Data input and outputbuffer circuitry 960 is included for bi-directional data communicationover a plurality of data (DQ) connections 962 with the processor 910,and is connected to write circuitry 955 and read/latch circuitry 950 forperforming read and write operations on the memory 900.

Command control circuit 970 decodes signals provided on controlconnections 972 from the processor 910. These signals are used tocontrol the operations on the memory array 930, including data read,data write, and erase operations. The flash memory device has beensimplified to facilitate a basic understanding of the features of thememory. A more detailed understanding of internal circuitry andfunctions of flash memories are known to those skilled in the art.

FIG. 10 is an illustration of an exemplary memory module 1000. Memorymodule 1000 is illustrated as a memory card, although the conceptsdiscussed with reference to memory module 1000 are applicable to othertypes of removable or portable memory, e.g., USB flash drives, and areintended to be within the scope of “memory module” as used herein. Inaddition, although one example form factor is depicted in FIG. 10, theseconcepts are applicable to other form factors as well.

In some embodiments, memory module 1000 will include a housing 1005 (asdepicted) to enclose one or more memory devices 1010, though such ahousing is not essential to all devices or device applications. At leastone memory device 1010 is a non-volatile memory including suspended gatenon-volatile memory cells and arrays according to various embodiments ofthe present invention. Where present, the housing 1005 includes one ormore contacts 1015 for communication with a host device. Examples ofhost devices include digital cameras, digital recording and playbackdevices, PDAs, personal computers, memory card readers, interface hubsand the like. For some embodiments, the contacts 1015 are in the form ofa standardized interface. For example, with a USB flash drive, thecontacts 1015 might be in the form of a USB Type-A male connector. Forsome embodiments, the contacts 1015 are in the form of asemi-proprietary interface. In general, however, contacts 1015 providean interface for passing control, address and/or data signals betweenthe memory module 1000 and a host having compatible receptors for thecontacts 1015.

The memory module 1000 may optionally include additional circuitry 1020which may be one or more integrated circuits and/or discrete components.For some embodiments, the additional circuitry 1020 may include a memorycontroller for controlling access across multiple memory devices 1010and/or for providing a translation layer between an external host and amemory device 1010. For example, there may not be a one-to-onecorrespondence between the number of contacts 1015 and a number of I/Oconnections to the one or more memory devices 1010. Thus, a memorycontroller could selectively couple an I/O connection (not shown in FIG.10) of a memory device 1010 to receive the appropriate signal at theappropriate I/O connection at the appropriate time or to provide theappropriate signal at the appropriate contact 1015 at the appropriatetime. Similarly, the communication protocol between a host and thememory module 1000 may be different than what is required for access ofa memory device 1010. A memory controller could then translate thecommand sequences received from a host into the appropriate commandsequences to achieve the desired access to the memory device 1010. Suchtranslation may further include changes in signal voltage levels inaddition to command sequences.

The additional circuitry 1020 may further include functionalityunrelated to control of a memory device 1010 such as logic functions asmight be performed by an ASIC (application specific integrated circuit).Also, the additional circuitry 1020 may include circuitry to restrictread or write access to the memory module 1000, such as passwordprotection, biometrics or the like. The additional circuitry 1020 mayinclude circuitry to indicate a status of the memory module 1000. Forexample, the additional circuitry 1020 may include functionality todetermine whether power is being supplied to the memory module 1000 andwhether the memory module 1000 is currently being accessed, and todisplay an indication of its status, such as a solid light while poweredand a flashing light while being accessed. The additional circuitry 1020may further include passive devices, such as decoupling capacitors tohelp regulate power requirements within the memory module 1000.

A MEM suspended gate non-volatile memory cell 1100 according to anotherembodiment is shown in side elevation in FIG. 11. The cell 1100comprises a substrate 1102 having source 1104 and drain 1106 regions. Asuspended structure 1110 has a carrier storage node (or floating gate)1112 surrounded by a dielectric layer 1111, and a control gate 1116. Thedielectric layer 1111 serves as a dielectric 1114 separating the carrierstorage node 1114 and the control gate 1116, as well as a tunnel oxidelayer 1108 which separates the substrate 1102, and source and drainregions 1104 and 1106 from the carrier storage node 1112 when thesuspended portion 1110 is moved to contact the substrate 1102. There isno tunnel oxide on the substrate 1102, and the dielectric 1108 on thesuspended portion 1110 serves as the tunnel oxide for the memory cell1100. The suspended structure 1110 is movable between a first positionwith an air or vacuum gap 1118 between the tunnel oxide 1108 and thesubstrate 1102, and a second position in which the suspended structuretunnel oxide 1108 contacts the substrate 1102.

Another MEM suspended gate non-volatile memory cell 1200 shown in FIG.12 differs from memory cell 1100 only in that a tunnel oxide layer 1208is also present over the substrate 1102, source 1104, and drain 1106regions.

CONCLUSION

A suspended gate non-volatile memory cell and array structures of cellshave been described that include a carrier storage node on a suspendedportion of a suspended gate MEM type structure.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiment shown. This applicationis intended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A non-volatile suspended gate memory cell, comprising: a substratehaving a pull-in/pull-out gate (PPG), source and drain regions, and atunnel oxide over the substrate; and a suspended gate movable between afirst position having a gap between the suspended gate and the tunneloxide, and a second position having no gap between the suspended gateand the tunnel oxide.
 2. The memory cell of claim 1, wherein thesuspended gate comprises: a carrier storage node; a control gate; and adielectric separating the carrier storage node and the control gate. 3.A non-volatile suspended gate memory cell, comprising: a substratehaving a pull-in/pull-out gate (PPG), source and drain regions, and atunnel oxide over the substrate; and a suspended gate comprising acarrier storage node, a control gate, and a dielectric separating thecarrier storage node and the control gate.
 4. The memory cell of claim3, wherein the PPG controls movement of the suspended gate from a firstposition having a gap between the carrier storage node and the tunneloxide, to a second position having no gap between the carrier storagenode and the tunnel oxide.
 5. The memory cell of claim 3, wherein thecarrier storage node is a floating gate.
 6. A non-volatile suspendedgate memory array, comprising: an array of suspended gate memory cellsarranged in rows and columns and accessed by bitlines and word lines;control circuitry to read, program, and erase the memory cells; andaddress circuitry to latch address signals provided on address inputconnections; wherein each memory cell comprises: a substrate having apull-in/pull-out gate (PPG), source and drain regions, and a tunneloxide over the substrate; and a suspended gate having a carrier storagenode and a control gate thereon, the suspended gate movable between afirst in which it is separated from the substrate by a gap, and a secondposition in which it contacts the dielectric.
 7. A method of fabricatinga non-volatile memory cell, comprising: forming a source region and adrain region in a tunnel oxide covered substrate; and suspending acarrier storage node, a dielectric layer, and a control gate above thetunnel oxide covered substrate.
 8. The method of claim 7, and furthercomprising: forming a pull-in/pull-out gate in the substrate.
 9. Amethod of fabricating a non-volatile memory, comprising: forming acarrier storage node on a suspended gate structure having a control gateand a dielectric separating the carrier storage node and the controlgate; and forming a pull-in/pull-out gate and source and drain regionsin a substrate covered by a tunnel dielectric.
 10. A method offabricating a non-volatile memory cell, comprising: forming a carrierstorage node on a suspended gate structure having a control gate, thecarrier storage node surrounded by a dielectric; and forming source anddrain regions in a substrate.
 11. The method of claim 10, and furthercomprising: forming a pull-in/pull-out gate in the substrate.
 12. Themethod of claim 10, and further comprising: forming a tunnel oxide overthe substrate.
 13. A method of operating a suspended gate non-volatilememory cell, comprising: moving a suspended gate having a carrierstorage node and a control gate separated by a dielectric between afirst position in which a gap separates the carrier storage node and atunnel oxide covered substrate and a second position in which thecarrier storage node contacts the tunnel oxide.
 14. The method of claim13, wherein the suspended gate is moved to the first position when nooperation is being performed on the memory.
 15. The method of claim 13,wherein the suspended gate is moved to the second position when aprogram, read, or erase operation is being performed on the memory. 16.The method of claim 13, wherein the suspended gate is moved to the firstposition by the application of a pull-out voltage to a pull-in/pull-outgate in the substrate.
 17. The method of claim 13, wherein the suspendedgate is moved to the second position by the application of a pull-involtage to a pull-in/pull-out gate in the substrate.
 18. The method ofclaim 13, and further comprising: programming the cell by moving thesuspended gate to the second position; applying set of program voltagesto the control gate and a drain and a source of the cell; and injectingelectrons from an active area of the substrate to the carrier storagenode.
 19. The method of claim 18, wherein moving the suspended gate tothe second position comprises applying a pull-in voltage to apull-in/pull-out gate in the substrate.
 20. The method of claim 13, andfurther comprising: reading the cell by moving the suspended gate to thesecond position; applying a set of read voltages to the control gate, asource and a drain of the cell, and the substrate; and reading a programstate of the carrier storage node.
 21. The method of claim 20, whereinmoving the suspended gate to the second position comprises applying apull-in voltage to a pull-in/pull-out gate in the substrate.
 22. Themethod of claim 13, and further comprising: erasing the cell by movingthe suspended gate to the second position; applying a set of erasevoltages to the control gate and the substrate; floating a source and adrain; and ejecting electrons from the carrier storage node to thesubstrate.
 23. The method of claim 22, wherein moving the suspended gateto the second position comprises applying a pull-in voltage to apull-in/pull-out gate in the substrate.
 24. A memory device, comprising:an array of suspended gate memory cells arranged in rows and columnssuch that the rows are each coupled to a word line and the columns areeach coupled to a bitline; control circuitry to read, write and erasethe memory cells; address circuitry to latch address signals provided onaddress input connections; wherein each memory cell comprises: asubstrate having a pull-in/pull-out gate (PPG), source and drainregions, and a tunnel oxide over the substrate; and a suspended gatecomprising a carrier storage node, a control gate, and a dielectricseparating the carrier storage node and the control gate.
 25. A memorydevice, comprising: an array of suspended gate memory cells arranged inrows and columns such that the rows are each coupled to a word line andthe columns are each coupled to a bitline; control circuitry to read,write and erase the memory cells; address circuitry to latch addresssignals provided on address input connections; wherein each memory cellcomprises: a substrate having a pull-in/pull-out gate (PPG), source anddrain regions, and a tunnel oxide over the substrate; and a suspendedgate having a carrier storage node, a control gate, and a dielectricseparating the carrier storage node and the control gate, the suspendedgate movable between a first position having a gap between the carrierstorage node and the tunnel oxide, and a second position having no gapbetween the carrier storage node and the tunnel oxide.
 26. A memorymodule, comprising: a plurality of contacts; and two or more memorydevices, each having access lines selectively coupled to the pluralityof contacts, wherein at least one of the memory devices comprises: anarray of non-volatile memory cells arranged in rows and columns andaccessed by bitlines and word lines; control circuitry to read, writeand erase the memory cells; and address circuitry to latch addresssignals provided on address input connections; wherein each memory cellcomprises: a substrate having a pull-in/pull-out gate (PPG), source anddrain regions, and a tunnel oxide over the substrate; and a suspendedgate comprising a carrier storage node, a control gate, and a dielectricseparating the carrier storage node and the control gate.
 27. A flashmemory module, comprising: a housing having a plurality of contacts; andone or more flash memory devices enclosed in the housing and selectivelycoupled to the plurality of contacts; wherein at least one of the memorydevices comprises: an array of non-volatile memory cells arranged inrows and columns and accessed by bitlines and word lines; controlcircuitry to read, write and erase the memory cells; and addresscircuitry to latch address signals provided on address inputconnections; wherein each memory cell comprises: a suspended gate havinga carrier storage node, a control gate, and a dielectric separating thecarrier storage node and the control gate, the suspended gate movablebetween a first position having a gap between the carrier storage nodeand the tunnel oxide, and a second position having no gap between thecarrier storage node and the tunnel oxide.
 28. A processing system,comprising: a processor; and a memory device coupled to the processor tostore data provided by the processor and to provide data to theprocessor, the memory comprising: an array of floating gate memory cellsarranged in rows and columns and accessed by bitlines and word lines, apair of memory cells sharing a common source/drain region; controlcircuitry to read, write and erase the memory cells; and addresscircuitry to latch address signals provided on address inputconnections; wherein each memory cell comprises: a substrate having apull-in/pull-out gate (PPG), source and drain regions, and a tunneloxide over the substrate; and a suspended gate comprising a carrierstorage node, a control gate, and a dielectric separating the carrierstorage node and the control gate.
 29. A non-volatile suspended gatememory cell, comprising: a substrate having source and drain regions,and a tunnel oxide over the substrate; and a suspended gate movablebetween a first position having a gap between the suspended gate and thetunnel oxide, and a second position having no gap between the suspendedgate and the tunnel oxide.
 30. The memory cell of claim 29, wherein thesuspended gate comprises: a carrier storage node; a control gate; and adielectric separating the carrier storage node and the control gate. 31.A non-volatile suspended gate memory cell, comprising: a substratehaving source and drain regions, and a tunnel oxide over the substrate;and a suspended gate comprising a carrier storage node, a control gate,and a dielectric separating the carrier storage node and the controlgate.
 32. A non-volatile suspended gate memory cell, comprising: asubstrate having source and drain regions; and a suspended gate movablebetween a first position having a gap between the suspended gate and thetunnel oxide, and a second position having no gap between the suspendedgate and the tunnel oxide, the suspended gate comprising: a carrierstorage node; a control gate; and a dielectric surrounding the carrierstorage node and separating the carrier storage node and the controlgate.
 33. The memory cell of claim 32, and further comprising: a tunneloxide over the substrate.
 34. The memory cell of claim 32, and furthercomprising: a pull-in/pull-out gate in the substrate.